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Preliminary Technical Data
FEATURES
105 MSPS guaranteed sampling rate (AD9460-105) 78.3 dBFS SNR with 30 MHz input (3.4 V p-p input, 80 MSPS) 76.6 dBFS SNR with 170 MHz input (3.4V p-p input, 80 MSPS) 90 dBc SFDR with 30 MHz input (3.4V p-p input, 105 MSPS) 83dBc SFDR with 225 MHz input (3.4V p-p input, 105 MSPS) 60 fsec rms jitter Excellent linearity DNL = 0.6 LSB typical INL = 4.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available 3.3 V and 5 V supply operation
16-Bit, 80 / 105 MSPS ADC AD9460
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD DFS DCS MODE BUFFER VIN+ VIN- T/H PIPELINE ADC 16 2 CMOS OR 32 LVDS OUTPUT STAGING 2 OUTPUT MODE OR D15 TO D0
AD9460
CLK+ CLK-
CLOCK AND TIMING MANAGEMENT
DCO REF
VREF SENSE REFT REFB
Figure 1.
APPLICATIONS
MRI receivers Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation
Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. The AD9460 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range -40C to +85C.
PRODUCT HIGHLIGHTS
1. True 16-bit linearity. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture. Packaged in a Pb-free, 100-lead TQFP/EP package. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.
GENERAL DESCRIPTION
The AD9460 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates up to 105 MSPS, providing superior SNR for instrumentation, medical imaging, and radar receivers employing baseband (<100 MHz) and IF frequencies. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.
2.
3.
4. 5. 6.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved.
AD9460 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications .................... Error! Bookmark not defined. AC Specifications..................... Error! Bookmark not defined. Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Terminology ...................................................................................... 9
Preliminary Technical Data
Pin Configurations and Function Descriptions ......................... 10 Equivalent Circuits......................................................................... 15 Typical Performance Characteristics ........ Error! Bookmark not defined. Theory of Operation ...................................................................... 16 Analog Input and Reference Overview ................................... 16 Clock Input Considerations...................................................... 18 Power Considerations................................................................ 19 Digital Outputs ........................................................................... 19 Timing ......................................................................................... 19 Operational Mode Selection ..................................................... 20 Evaluation Board ............................................................................ 21 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
10/05--Revision 0: Initial Version
Rev. PrA| Page 2 of 28
Preliminary Technical Data DC SPECIFICATIONS
AD9460
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = -1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL)1 Integral Nonlinearity (INL)1 VOLTAGE REFERENCE Output Voltage VREF = 1.7V Load Regulation @ 1.0 mA Reference Input Current (External VREF = 1.7 V) INPUT REFERRED NOISE ANALOG INPUT Input Span VREF = 1.7V VREF = 1.0 V Internal Input Common-Mode Voltage External Input Common-Mode Voltage Input Resistance2 Input Capacitance2 POWER SUPPLIES Supply Voltage AVDD1 AVDD2 DRVDD--LVDS Outputs DRVDD--CMOS Outputs Supply Current1 AVDD1 AVDD21, 3 IDRVDD1--LVDS Outputs IDRVDD1--CMOS Outputs PSRR Offset Gain POWER CONSUMPTION LVDS Outputs CMOS Outputs (DC Input)
1 2
Temp Full Full Full 25C Full 25C Full 25C Full Full Full Full 25C
Min
AD9460BSVZ-80 Typ Max 16 Guaranteed 3
AD9460BSVZ-105 Min Typ Max 16
Unit Bits
3
0.6 4.0
0.6 4.0
mV mV % FSR % FSR LSB LSB LSB V mV A LSB rms
1.7 2
1.7 2
Full Full Full Full Full Full
3.4 2.0 3.5 3.2 1 6 3.9 3.2
3.4 2.0 3.5 3.9 1 6
V p-p V p-p V V k pF
Full Full Full Full Full Full Full Full Full Full Full Full
3.14 4.75 3.0 3.0
3.3 5.0 3.3 270
103
3.46 5.25 3.6 3.6
3.14 4.75 3.0 3.0
3.3 5.0 3.3 310
120
3.46 5.25 3.6 3.6
V V V V mA mA mA mA mV/V %/V W W
63 14 1 0.2 1.6 1.4
63 14 1 0.2
1.8 1.6
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.
Rev.PrA | Page 3 of 28
AD9460
AC SPECIFICATIONS
Preliminary Technical Data
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), AIN = -1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted. Table 2.
Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz fIN = 30 MHz fIN = 170 MHz fIN = 225 MHz1 fIN = 300 MHz2 fIN = 400 MHz2 fIN = 450 MHz2 fIN = 10 MHz (2.0 V p-p Input) fIN = 30 MHz (2.0 V p-p Input) fIN = 170 MHz (2.0 V p-p Input) fIN = 225 MHz (2.0 V p-p Input)1 fIN = 300 MHz (2.0 V p-p Input)2 SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz fIN = 30 MHz fIN = 170 MHz fIN = 225 MHz1 fIN = 300 MHz2 fIN = 400 MHz2 fIN = 450 MHz2 fIN = 10 MHz(2.0 V p-p Input) fIN = 30 MHz (2.0 V p-p Input) fIN = 170 MHz (2.0 V p-p Input) fIN = 225 MHz (2.0 V p-p Input) fIN = 300 MHz (2.0 V p-p Input) EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 30 MHz fIN = 170 MHz fIN = 225 MHz1 fIN = 300 MHz2 fIN = 400 MHz2 fIN = 450 MHz2 Temp 25C 25C Full 25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full 25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 12.8 12.7 12.5 12.0 12.7 12.4 12.2 78.1 77.1 75.9 73.3 77.8 Min AD9460BSVZ-80 Typ Max 78.3 77.7 76.6 75.5 Min AD9460BSVZ-105 Typ Max 77.9 77.8 76.2 75.4 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits Bits Bits
75.4 74.3
Rev. PrA| Page 4 of 28
Preliminary Technical Data
Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR, Second or Third Harmonic) fIN = 10 MHz fIN = 30 MHz fIN = 170 MHz fIN = 225 MHz1 fIN = 300 MHz2 fIN = 400 MHz2 fIN = 450 MHz2 fIN = 10 MHz(2.0 V p-p Input) fIN = 30 MHz (2.0 V p-p Input) fIN = 170 MHz (2.0 V p-p Input) fIN = 225 MHz (2.0 V p-p Input) fIN = 300 MHz (2.0 V p-p Input) WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz fIN = 30 MHz fIN = 170 MHz fIN = 225 MHz1 fIN = 300 MHz2 fIN = 400 MHz2 fIN = 450 MHz2 fIN = 10 MHz(2.0 V p-p Input) fIN = 30 MHz (2.0 V p-p Input) fIN = 170 MHz (2.0 V p-p Input) fIN = 225 MHz (2.0 V p-p Input) fIN = 300 MHz (2.0 V p-p Input) TWO-TONE SFDR fIN = 30.3 MHz @ -7 dBFS, 31.3 MHz @ -7 dBFS fIN = 170.3 MHz @ -7 dBFS, 171.3 MHz @ -7 dBFS ANALOG BANDWIDTH
1 2
AD9460
Temp Min AD9460BSVZ-80 Typ Max Min AD9460BSVZ-105 Typ Max Unit
25C 25C Full 25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C
93 87 84 80
90 90 84 83
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
25C 25C Full 25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full
97 97 96 96
92
92 86
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS MHz
TBD RF ENABLE = high (AVDD1).
Rev.PrA | Page 5 of 28
AD9460
DIGITAL SPECIFICATIONS
Preliminary Technical Data
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 k, unless otherwise noted. Table 3.
Parameter CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS--CMOS MODE (D0 to D15, OTR)1 DRVDD = 3.3 V High Level Output Voltage Low Level Output Voltage DIGITAL OUTPUT BITS--LVDS MODE (D0 to D15, OTR) VOD Differential Output Voltage2 VOS Output Offset Voltage CLOCK INPUTS (CLK+, CLK-) Differential Input Voltage Common-Mode Voltage Input Resistance Input Capacitance
1 2
Temp Full Full Full Full Full
AD9460BSVZ-80 Min Typ Max 2.0 0.8 200 +10 2
Unit V V A A pF
-10
Full Full Full Full Full Full Full Full
3.25 0.2 247 1.125 0.2 1.3 1.1 545 1.375
V V mV V V V k pF
1.5 1.4 2
1.6 1.7
Output voltage levels measured with 5 pF load on each output. LVDS RTERM = 100 .
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High1 (tCLKH) CLK Pulse Width Low1 (tCLKL) DATA OUTPUT PARAMETERS Output Propagation Delay--CMOS (tPD)2 (Dx, DCO+) Output Propagation Delay--LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ)
1 2 3
Temp Full Full Full Full Full Full Full Full Full Full
AD9460BSVZ-80 Min Typ Max 80 1 12.5 5.0 5.0 3.35 3.6 13 60
Unit MSPS MSPS ns ns ns ns ns Cycles ns fsec rms
2.1
4.8
With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
Rev. PrA| Page 6 of 28
Preliminary Technical Data
TIMING DIAGRAMS
N-1 AIN N N+1
AD9460
tCLKL tCLKH
1/fS CLK+ CLK-
tPD
DATA OUT N - 13 N - 12 13 CLOCK CYCLES DCO+ DCO-
05490-002
N
N+1
tCPD
Figure 2. LVDS Mode Timing Diagram
N-1 N N+1 VIN
tCLKL tCLKH
CLK-
N+2
CLK+
tPD
13 CLOCK CYCLES
DX
N - 13
N - 12
N-1
N
DCO+ DCO-
05490-003
Figure 3. CMOS Timing Diagram
Rev.PrA | Page 7 of 28
AD9460 ABSOLUTE MAXIMUM RATINGS
Table 5.
With Respect to AGND AGND DGND DGND DRVDD DRVDD AVDD1 DGND AGND AGND AGND AGND AGND AGND
Preliminary Technical Data
Parameter ELECTRICAL AVDD1 AVDD2 DRVDD AGND AVDD1 AVDD2 AVDD2 D0 to D15 CLK+/CLK- OUTPUT MODE, DCS MODE, DFS VIN+, VIN- VREF SENSE REFT, REFB ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature
Rating -0.3 V to +4 V -0.3 V to +6 V -0.3 V to +4 V -0.3 V to +0.3 V -4 V to +4 V -4 V to +6 V -4 V to +6 V -0.3 V to DRVDD + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to AVDD2 + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to AVDD1 + 0.3 V -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
The heat sink of the AD9460 package must be soldered to ground. Table 6.
Package Type 100-lead TQFP/EP JA 19.8 JB 8.3 JC 2 Unit C/W
Typical JA = 19.8C/W (heat sink soldered) for multilayer board in still air. Typical JB = 8.3C/W (heat sink soldered) for multilayer board in still air. Typical JC = 2C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path. Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the JA. It is required that the exposed heat sink be soldered to the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA| Page 8 of 28
Preliminary Technical Data TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:
AD9460
Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value of 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
ENOB =
(SINAD - 1.76 )
6.02
Gain Error The first code transition should occur at an analog value of 1/2 LSB above negative full scale. The last transition should occur at an analog value of 11/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Maximum Conversion Rate The clock rate at which parametric testing is performed.
Rev.PrA | Page 9 of 28
AD9460 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D15+ (MSB) DRGND DRVDD
Preliminary Technical Data
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1 DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND
2 3 4 5 6 7 8 9 PIN 1
DRVDD
75 74 73 72 71 70
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
AGND
D14+
D13+
D12+
D11+
D15-
D13-
D12-
D11-
D14-
OR+
OR-
DRGND D10+ D10- D9+ D9- D8+ D8- DCO+ DCO- D7+ D7- DRVDD DRGND D6+ D6- D5+ D5- D4+ D4- D3+ D3- D2+ D2- D1+ D1-
AD9446 LVDS MODE
TOP VIEW (Not to Scale)
AD9460
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
REFT 10 REFB 11 AVDD2 12 AVDD2 13 AVDD2 14 AVDD2 15 AVDD2 16 AVDD2 17 AVDD1 18 AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN- 23 AGND 24 AVDD2 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D0- (LSB)
AGND
AGND
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
AGND
CLK+
CLK-
DRGND
DRVDD
D0+
DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. PrA| Page 10 of 28
05490-004
Preliminary Technical Data
Table 7. Pin Function Descriptions--100-Lead TQFP/EP in LVDS Mode
Pin No. 1 2 3 4 5 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 7 8 9, 21, 24, 39, 42, 46, 91, 98, 99, 100, Exposed Heat Sink 10 11 12 to 17, 25 to 31, 35, 37 22 23 40 41 47, 63, 75, 87, 48, 64, 76, 88 49 50 51 52 53 54 55 56 57 58 59 60 61 62 65 66 67 68 69 70 71 72 73 74 77 78 Mnemonic DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD D0- (LSB) D0+ D1- D1+ D2- D2+ D3- D3+ D4- D4+ D5- D5+ D6- D6+ D7- D7+ DCO- DCO+ D8- D8+ D9- D9+ D10- D10+ D11- D11+
AD9460
Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended); DCS = high (AVDD1) to disable DCS. Do Not Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode; OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 3.3 V (5%) Analog Supply. Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference. 1.7 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 11) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 10) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement. Clock Input--True. Clock Input--Complement. Digital Output Ground. 3.3 V Digital Output Supply (3.0 V to 3.6 V). D0 Complement Output Bit (LVDS Levels). D0 True Output Bit. D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. Data Clock Output--Complement. Data Clock Output--True. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit.
Rev.PrA | Page 11 of 28
AD9460
Pin No. 79 80 81 82 83 84 85 86 89 90 Mnemonic D12- D12+ D13- D13+ D14- D14+ D15- D15+ (MSB) OR- OR+ Description D12 Complement Output Bit. D12 True Output Bit. D13 Complement Output Bit D13 True Output Bit. D14 Complement Output Bit D14 True Output Bit. D15 Complement Output Bit. D15 True Output Bit. Out-of-Range Complement Output Bit. Out-of-Range True Output Bit.
Preliminary Technical Data
Rev. PrA| Page 12 of 28
Preliminary Technical Data
D15+ (MSB) DRGND DRVDD DRVDD AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND AGND AGND D14+ D13+ D12+ D11+ D10+
AD9460
OR+
D9+
D8+
D7+
D6+
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1 DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND
2 3 4 5 6 7 8 9 PIN 1
D5+
75 74 73 72 71 70
DRGND D4+ D3+ D2+ D1+ D0+ (LSB) DNC DCO+ DCO- DNC DNC DRVDD DRGND DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC
AD9446 CMOS MODE
TOP VIEW (Not to Scale)
AD9460
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
REFT 10 REFB 11 AVDD2 12 AVDD2 13 AVDD2 14 AVDD2 15 AVDD2 16 AVDD2 17 AVDD1 18 AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN- 23 AGND 24 AVDD2 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
CLK+
CLK-
DNC
DRGND
DRVDD
AGND
AGND
AGND
DNC
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev.PrA | Page 13 of 28
05490-005
AD9460
Table 8. Pin Function Descriptions--100-Lead TQFP/EP in CMOS Mode
Pin No. 1 2, 49 to 62, 65 to 66, 69, 3 4 5 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 7 8 9, 21, 24, 39, 42, 46, 91, 98, 99, 100, Exposed Heat Sink 10 11 12 to 17, 25 to 31, 35, 37 22 23 40 41 47, 63, 75, 87, 48, 64, 76, 88 67 68 70 71 72 73 74 77 78 79 80 81 82 83 84 85 86 89 90 Mnemonic DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND
Preliminary Technical Data
Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended); DCS = high (AVDD1) to disable DCS. Do Not Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode; OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 3.3 V (5%) Analog Supply. Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference. 1.7 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 11) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 10) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement. Clock Input--True. Clock Input--Complement. Digital Output Ground. 3.3 V Digital Output Supply (3.0 V to 3.6 V). Data Clock Output--Complement. Data Clock Output--True. D0 True Output Bit (CMOS levels). D1 True Output Bit. D2 True Output Bit. D3 True Output Bit. D4 True Output Bit. D5 True Output Bit. D6 True Output Bit. D7 True Output Bit. D8 True Output Bit. D9 True Output Bit. D10 True Output Bit. D11 True Output Bit. D12 True Output Bit. D13 True Output Bit. D14 True Output Bit. D15 True Output Bit. Out-of-Range True Output Bit.
REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD DCO- DCO+ D0+ (LSB) D1+ D2+ D3+ D4+ D5+ D6+ D7+ D8+ D9+ D10+ D11+ D12+ D13+ D14+ D15+ (MSB) OR+
Rev. PrA| Page 14 of 28
Preliminary Technical Data EQUIVALENT CIRCUITS
AVDD2 VIN+ 6pF 1k
DRVDD
AD9460
3.5V
X1 1k
T/H
AVDD2
DX
VIN-
05490-006
6pF
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
05490-009
VDD
DRVDD DRVDD
1.2V LVDSBIAS 3.74k
K
DCS MODE, OUTPUT MODE, DFS
30k
05490-007
ILVDSOUT
Figure 7. Equivalent LVDS_BIAS Circuit
Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE
AVDD1
DRVDD
3k CLK+
V DX- V V DX+ V
3k CLK-
2.5k
2.5k
05490-008
05490-010
05490-011
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev.PrA | Page 15 of 28
AD9460 THEORY OF OPERATION
The AD9460 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 16-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.
Preliminary Technical Data
<2 V p-p. However, reducing the range can improve SFDR performance in some applications. Likewise, increasing the range up to 3.4 V p-p can improve SNR. Users are cautioned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations that use <2.0 V p-p may exhibit missing codes and therefore degraded noise and distortion performance.
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F SELECT LOGIC SENSE 0.5V 0.1F +
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V band gap voltage reference is built into the AD9460. The input range can be adjusted by varying the reference voltage applied to the AD9460, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.
10F
Internal Reference Connection
A comparator within the AD9460 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 12), setting VREF to ~1.7 V. If a resistor divider is connected as shown in Figure 13, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
R2 VREF = 0.5 V x 1 + R1 In all reference configurations, REFT and REFB drive the analog-to-digital conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
AD9460 AD9446 Figure 12. Internal Reference Configuration
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF + 10F 0.1F R2 SENSE SELECT LOGIC 0.1F +
10F
Internal Reference Trim
The internal reference voltage is trimmed during the production test; therefore, there is little advantage to the user supplying an external voltage reference to the AD9460. The gain trim is performed with the AD9460 input range set to 3.4 V p-p nominal (SENSE connected to AGND). Because of this trim and the maximum ac performance provided by the 3.4 V p-p analog input range, there is little benefit to using analog input ranges
R1
0.5V
AD9446 AD9460
Figure 13. Programmable Reference Configuration
Rev. PrA| Page 16 of 28
05490-053
05490-052
Preliminary Technical Data
Table 9. Reference Configuration Summary
Selected Mode External Reference Programmable Reference Programmable Reference (Set for 2 V p-p) Internal Fixed Reference SENSE Voltage AVDD 0.2 V to VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A
R2 (See Figure 13) 0.5 x 1 + R1 R2 , R1 = R2 = 1 k 0.5 x 1 + R1
AD9460
Resulting Differential Span (V p-p) 2 x external reference 2 x VREF 2.0 3.4
1.7
External Reference Operation
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 2.0 V. See Error! Reference source not found. for gain variation vs. temperature.
VIN+
1.7V p-p
3.5V
VIN-
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
Analog Inputs
As with most new high speed, high dynamic range ADCs, the analog input to the AD9460 is differential. Differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD9460 cannot be realized with a single-ended analog input, so such configurations are discouraged. Contact sales for recommendations of other 16-bit ADCs that support singleended analog input configurations. With the 1.7 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9460 analog input is nominally 3.4 V p-p or 1.7 V p-p on each input (VIN+ or VIN-).
05490-054
Figure 14. Differential Analog Input Range for VREF = 1.7 V
The AD9460 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 k resistor to the 3.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD9460 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9460 is to use an RF transformer to convert single-ended signals to differential (see Figure 15). Series resistors between the output of the transformer and the AD9460 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the 1 k resisters connected to the internal 3.5 V bias, must be considered in impedance matching the transformer input. For example, if RT is set to 51 , RS is set to 33 and there is a 1:1 impedance ratio transformer, the input will match a 50 source with a full-scale drive of 16.0 dBm. The 50 impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 18).
Rev.PrA | Page 17 of 28
AD9460
ANALOG INPUT SIGNAL RT ADT1-1WT RS VIN+
Preliminary Technical Data
AD9460 AD9446
05490-055
RS
0.1F
VIN-
Figure 15. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-todigital output. For that reason, considerable care was taken in the design of the clock inputs of the AD9460, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9460 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal ~50% duty cycle. Noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 30 MHz nominally. The loop is associated with a time constant that should be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such an application, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller. The AD9460 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 16-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. (See the AN-501 Application Note, "Aperture Uncertainty and ADC System Performance.") For optimum performance, the AD9460 must be clocked differentially. The sample clock inputs are internally biased to ~1.5 V, and the input signal is usually ac-coupled into the CLK+ and CLK- pins
via a transformer or capacitors. Figure 16 shows one preferred method for clocking the AD9460. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary of the transformer limit clock excursions into the AD9460 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9460 and limits the noise presented to the sample clock inputs. If a low jitter clock is available, it may help to band-pass filter the clock reference before driving the ADC clock inputs. Another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 17.
CRYSTAL SINE SOURCE ADT1-1WT
0.1F
CLK+
AD9446 AD9460
HSMS2812 DIODES
05490-056
CLK-
Figure 16. Crystal Clock Oscillator, Differential Encode
VT
0.1F
ENCODE ECL/ PECL 0.1F
AD9446 AD9460
ENCODE
05490-057
VT
Figure 17. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) and rms amplitude due only to aperture jitter (tJ) can be calculated using the following equation:
SNR = 20 log[2fINPUT x tJ]
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9460. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be synchronized by the original clock during the last step.
Rev. PrA| Page 18 of 28
Preliminary Technical Data
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9460. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD9460 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V), and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies can be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9460 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply can be connected from 2.5 V to 3.6 V for compatibility with the receiving logic.
AD9460
data clock output (DCO+/DCO-). The RSET resistor current is multiplied on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 x IRSET). A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended, with a 100 termination resistor located as close to the receiver as possible. It is recommended to keep the trace length less than 2 inches and to keep differential output trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic performance, the AD9460 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits, Dx, are single-ended CMOS, as is the overrange output, OR+. The output clock is provided as a differential CMOS signal, DCO+/DCO-. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 ) to minimize switching transients caused by the capacitive loading.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 3 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 k RSET resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9460 is used in LVDS mode; designers are encouraged to take advantage of this mode. The AD9460 outputs include complimentary LVDS outputs for each data bit (Dx+/Dx-), the overrange output (OR+/OR-), and the output
TIMING
The AD9460 provides latched data outputs with a pipeline delay of 13 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and Figure 3 for detailed timing diagrams.
Rev.PrA | Page 19 of 28
AD9460
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9460 determines the coding format of the output data. This pin is 3.3 V CMOS compatible, with logic high (or AVDD1, 3.3 V) selecting twos complement and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding.
Preliminary Technical Data
compatible input. With OUTPUT MODE = 0 (AGND), the AD9460 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9460 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOS-
Table 10. Digital Output Coding
Code 65,536 32,768 32,767 0 VIN+ - VIN- Input Span = 3.4 V p-p (V) +1.700 0 -0.000052 -1.70 VIN+ - VIN- Input Span = 2 V p-p (V) +1.000 0 -0.000031 -1.00 Digital Output Offset Binary (D15******D0) 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 Digital Output Twos Complement (D15******D0) 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000
Rev. PrA| Page 20 of 28
Preliminary Technical Data EVALUATION BOARD
Evaluation boards are offered to configure the AD9460 in either CMOS or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of sampling rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics are shown in Figure 18 through Figure 21. Gerber files are available from engineering applications demonstrating the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (<60 fsec rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal to remove harmonics and lower the integrated noise at the input is also necessary to achieve the specified noise performance. The evaluation boards are shipped with a 115 V ac to 6 V dc power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD9460 and its support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 18).
AD9460
The LVDS mode evaluation boards include an LVDS-to-CMOS translator, making them compatible with the high speed ADC FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a high speed data capture board that provides a hardware solution for capturing up to 32 kB samples of high speed ADC output data in a FIFO memory chip (user upgradeable to 256 kB samples). Software is provided to enable the user to download the captured data to a PC via the USB port. This software also includes a behavioral model of the AD9460 and many other high speed ADCs. Behavioral modeling of the AD9460 is also available at www.analog.com/ADIsimADC. The ADIsimADCTM software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9460 and other high speed ADCs with or without hardware evaluation boards. The user can choose to remove the translator and terminations to access the LVDS outputs directly.
Rev.PrA | Page 21 of 28
AD9460
GND
P22 P21 PTMICRO4 PTMICRO4
DRGND 1 P1 2 P2 3 P3 4 P4 1 P1 2 P2 3 P3 4 P4 H2 MTHOLE6 GND VCC GND 5V H1 MTHOLE6 H3 MTHOLE6 H4 MTHOLE6 XTALPWR EXTREF DRGND DRVDD
VCC
E19
E66
GND
E18
VCC
E4
DRVDD D11_C/D6_Y D11_T/D7_Y
D12_C/D8_Y D12_T/D9_Y D13_C/D10_Y D13_T/D11_Y D14_C/D12_Y D14_T/D13_Y D15_C/D14_Y (MSB) D15_T/D15_Y DRGND DRVDD DOR_C DOR_T/DOR_Y GND VCC VCC VCC VCC VCC VCC GND
E6 GND
GND
E5
VCC
E10
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
E1
GND
E9
EPAD
DRVDD D11_C D11_T D12_C D12_T D13_C D13_T D14_C D14_T D15_C D15_T DRGND DRVDD OR_C OR_T AGND AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND AGND
VCC R11 1k GND
E3
E14 VCC
DRGND D10_T/D5_Y D10_C/D4_Y D9_T/D3_Y D9_C/D2_Y
GND
E2
GND VCC E41 E24 GND C3 0.1F C40 0.1F C9 0.1F GND C98 DNP GND C51 10F E25 E27 E26 C86 0.1F
Figure 18. AD9460 Evaluation Board Schematic
GND EXTREF GND
Rev. 0 | Page 22 of 28
+
GND C39 10F U1
5
R3 3.74k
R1 DNP
D8_T/D1_Y D8_C/D0_Y DR DRB
AD9460 AD9445/AD9446
R2 GND DNP
D7_T D7_C DRVDD DRGND D6_T D6_C
GND TOUT CT GND GND T2
1 4
R5 DNP C7 0.1F R4 36 R28 33
T1 ETC1-1-13
J4 SMBMST C12 0.1F
GND
1
L1 10nH
2
D0_T D0_C DRVDD DRGND AGND AVDD1 AVDD1 AVDD1 AGND ENCB
ENC AGND AVDD1 AVDD2 AVDD1 AVDD2 AVDD1 AVDD1 AVDD1 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2
C5 0.1F
TINB
3
PRI
SEC
SCLK 1 2 3 4 5 6 VCC 7 8 9 GND 10 11 12 5V C2 13 5V 0.1F 14 5V 5V 15 16 5V 17 5V 18 VCC 19 VCC 20 VCC 21 GND 22 23 24 GND 25 5V DCS MODE DNC OUTPUT MODE DFS LVDSBIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VIN- AGND AVDD2
DRGND D10_T D10_C D9_T D9_C D8_T D8_C DCO DCOB D7_T D7_C DRVDD DRGND D6_T D6_C D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C
PRI
3 4 2 5
ETC1-1-13
ANALOG R9 DNP R6 36
TOUTB
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
C13 DNP
SEC
OPTIONAL
E15
C91 0.1F
GND TOUT GND GND CT TOUTB C8 0.1F
T5 ADT1-1WT
ENCB ENC GND VCC 5V VCC 5V VCC VCC VCC
D0_T D0_C (LSB) DRVDD DRGND GND VCC VCC VCC GND
NC
1 5
6 2
5V
3
4
TINB
Preliminary Technical Data
05490-059
PRI
SEC
R35 33
GND GND R7 DNP VXTAL R39 0 E31 5V E30 E20 XTALPWR + C44 10F GND ENC VXTAL + C1 10F CR2 TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL C41 0.1F
ENCODE
OPTIONAL ENCODE CIRCUITS
3
T3 ADT1-1WT
CR2
CR1
Preliminary Technical Data
C36 DNP
1 NC 5 6 2
DNP GND
J1 SMBMST
3 4
1
J5 SMBMST
2
U6 ECLOSC 14 7 VCC VEE OUT ~OUT 8 1 XTALINPUT
2
C42 PRI SEC 0.1F GND
1
3
R8 50 ENCB GND GND DRVDD L4 FERRITE VCCX L3 FERRITE 5VX L5 FERRITE DRVDDX VXTAL
C26 0.1F
XTALINPUT
VCC
Figure 19. AD9460 Evaluation Board Schematic (Continued)
5V GND L2 DNP
Rev. 0 | Page 23 of 28
ADP3338
U14 5V GND GND GND 5VX VCCX VIN 4 OUT 5VX VIN IN 3 4 OUT OUT1 2 1
POWER OPTIONS
DRGND
ADP3338
U7 3.3V GND OUT1 IN 1 2 3 GND VCCX VIN DRVDDX 4
ADP3338
U3 3.3V GND OUT OUT1 IN 1 2 3 DRGND DRVDDX VIN
P4
PJ-102A
2
2
3
3
1
1
+ C33 10F + C89 10F GND GND + C34 10F
+ + C87 10F
C6 10F + C88 10F GND GND DRGND
+
C4 10F
GND
DRGND
05490-060
AD9460
AD9460
BYPASS CAPACITORS
VCC + GND C64 10F C43 0.1F C35 0.1F C32 0.1F C30 0.01F C28 0.1F C27 0.1F C90 0.1F C50 0.1F
Preliminary Technical Data
C60 0.1F
C10 0.1F
C61 0.1F
C75 0.1F
VCC C11 XX GND C14 XX C17 XX C16 XX C15 XX C31 XX C38 XX C29 XX C19 XX
DRVDD + DRGND C65 10F C47 0.1F C23 0.1F C21 0.1F C20 0.1F
DRVDD C69 XX DRGND C70 XX C45 XX C49 XX
5V + GND C56 10F C85 0.1F C53 0.1F C52 0.1F C58 0.01F C37 0.1F C48 0.1F C18 0.1F
EXTREF + GND C55 10F
5V C72 XX GND C73 XX C108 XX C109 XX C110 XX
5V
05490-061
C94 0.1F GND
C95 0.1F
C22 0.1F
C59 0.1F
C93 0.1F
C96 0.1F
C97 0.1F
C84 0.1F
C46 0.1F
Figure 20. AD9460 Evaluation Board Schematic (Continued)
Rev. 0 | Page 24 of 28
U15 SN75LVDT390 DR DRB DRVDD R19 DRVDD 0 DRGND R20 0 ORO DRVDD DRO 1 2 3 4 5 6 7 8 1A 1B 2A 2B 3A 3B 4A 4B EN_1_2 1Y 2Y VCC GND 3Y 4Y EN_3_4 16 15 14 13 12 11 10 9
DRO_T/DOR_Y DOR_C
Preliminary Technical Data
U8 SN75LVDS386 RZ5 220 RSO16ISO 1 2 3 4 DRVDD 5 6 7 8 R4 R5 R6 R7 R8 R3 14 13 12 11 10 9 220 RSO16ISO 1 2 DRVDD 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 RZ4 16 15 14 13 12 11 10 9 D7O D6O D5O D4O D3O D2O D1O D0O DRGND R2 15 R1 16 D15O D14O D13O D12O D11O D10O D9O D8O
DRGND DRGND DOR_C D15_C/D14_Y D14_C/D12_Y D13_C/D10_Y D12_C/D8_Y D11_C/D6_Y D10_C/D4_Y D9_C/D2_Y D8_C/DO_Y DRB D7_C D6_C D5_C D4_C D3_C D2_C D1_C D0_C DRGND
40
P40
P39 39
DRGND ORO
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
P39 39 P37 37 P35 35 P33 33 P31 31 P29 29 P27 27 P25 25 P23 23 P21 21 P19 19 P17 17 P15 15 P13 13 P11 11 P9 9 P7 7 P5 5 P3 3 P1 1 P7 C40MS
DRGND DRO GND?? D15O D14O D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O DRGND
DOR_T/DOR_Y
38
P38
P37 37
D15_T/D15_Y
36
P36
P35 35
DRGND DRVDD DRVDD DRGND DRVDD
D14_T/D13_Y
34
P34
P33 33
D13_T/D11_Y
32
P32
P31 31
D12_T/D9_Y
30
P30
P29 29
D11_T/D7_Y
28
P28
P27 27
D10_T/D5_Y
26
P26
P25 25
D9_T/D3_Y
24
P24
P23 23
Figure 21. AD9460 Evaluation Board Schematic (Continued)
Rev. 0 | Page 25 of 28
DRGND DRVDD DRVDD DRGND DRVDD DRGND DRVDD DRVDD DRGND GND C76 0.1F GND C82 0.1F C77 0.1F C78 0.1F
D8_T/D1_Y
22
P22
P21 21
DR
20
P20
P19 19
D7_T
18
P18
P17 17
D6_T
16
P16
P15 15
D5_T
14
P14
P13 13
D4_T
12
P12
P11 11
D3_T
10
P10
P9 9
D2_T
8
P8
P7 7
D1_T
6
P6
P5 5
D0_T
4
P4
P3 3
DRGND
2
P2
P1 1
D15_T/D14_Y D15_C/D14_Y D14_T/D13_Y D14_C/D12_Y D13_T/D11_Y D13_C/D10_Y D12_T/D9_Y D12_C/D8_Y D11_T/D7_Y D11_C/D6_Y D10_T/D5_Y D10_C/D4_Y D9_T/D3_Y D9_C/D2_Y D8_T/D1_Y D8_C/D0_Y D7_T D7_C D6_T D6_C D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C D0_T D0_C A1A A1B A2A A2B A3A A3B A4A A4B B1A B1B B2A B2B B3A B3B B4A B4B C1A C1B C2A C2B C3A C3B C4A C4B D1A D1B D2A D2B D3A D3B D4A D4B GND VCC1 VCC2 GND1 ENA A1Y A2Y A3Y A4Y ENB B1Y B2Y B3Y B4Y GND2 VCC3 VCC4 GND3 C1Y C2Y C3Y C4Y ENC D1Y D2Y D3Y D4Y END GND4 VCC5 VCC6 GND5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P6 C40MS
05490-062
AD9460
AD9460
Table 11. AD9460 Customer Evaluation Board Bill of Material
Item 1 2 Qty. 7 44 Reference Designator C4, C6, C33, C34, C87, C88, C89 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C97 C30, C58 C39, C56, C64, C65 C51 CR1 CR2 E1, E2, E3, E4, E5, E6, E9, E10, E14, E18, E19, E20, E24, E25, E26, E27, E30, E31, E36, E41 J1, J4 L1 L3, L4, L5 P4 P7 R3 R8 R10, R19, R39, L2 R11 R28, R35 RZ4, RZ5 T3, T5 U1 U14 U3, U7 U8 U15 R4, R6 C1, C44, C551 C13, C14, C16, C17, C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, C108, C109, C1101 C981 Description Capacitor Capacitor Package TAJD 402 Value 10 F 0.1 F
Preliminary Technical Data
Manufacturer Digi-Key Corporation Digi-Key Corporation Mfg. Part No. 478-1699-2 PCC2146CT-ND
3 4 5 6 7 8
2 4 1 1 1 20
Capacitor Capacitor Capacitor Diode Diode Header
201 TAJD 805 SOT23M5 SOT23M5 EHOLE
0.01 F 10 F 10 F
Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Mouser Electronics
445-1796-1-ND 478-1699-2 490-1717-1-ND MA3X71600LCTND MA3X71600LCTND 517-6111TG
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
2 1 3 1 1 1 1 4 1 2 2 2 1 1 2 1 1 2 2 23
SMA Inductor EMIFIL(R) BLM31PG500SN1L PJ-002A Header Resistor Resistor Resistor BRES402 Resistor Resistor array Transformer AD9445BSVZ-125 ADP3338-5 ADP3338-3.3 SN75LVDT386 SN75LVDT390 Resistor Capacitor CAP402
SMA 0603A 1206MIL PJ-002A C40MS 402 402 402 402 402 16PIN ADT1-1WT SV-100-3 SOT223HS SOT223HS TSSOP64 SOIC16PW 402 TAJD 402
10 nH
Digi-Key Corporation Coilcraft, Inc. Mouser Electronics Digi-Key Corporation Samtec, Inc.
ARFX1231-ND 0603CS-10NXGBU 81-BLM31P500S CP-002A-ND TSW-120-08-L-DRA P3.74KLCT-ND P49.9LCT-ND P0.0JCT-ND P1.0KLCT-ND P33JCT-ND 742C163220JCTND ADT1-1WT AD9460BSVZ ADP3338-5 ADP3338-33 SN75LVDT386 SN75LVDT390 P36JCT-ND 478-1699-2
3.74 k 50 0 1 k 33 22
Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Mini-Circuits Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Arrow Electronics, Inc. Arrow Electronics, Inc. Digi-Key Corporation Digi-Key Corporation
36 10 F XX
29
1
Capacitor
805
Rev. 0 | Page 26 of 28
10 F
Digi-Key Corporation
490-1717-1-ND
Preliminary Technical Data
Item 30 31 32 33 34 35 36 37 38
1
AD9460
Package EHOLE SMA C40MS 402 402 DIP4(14) MTHOLE6 SM-22 PTMICRO4 Value Manufacturer Mouser Electronics Digi-Key Corporation Samtec, Inc. Mfg. Part No. 517-6111TG ARFX1231-ND TSW-120-08-L-DRA
Qty.
Reference Designator E151 J51 P61 R1, R21 R5, R7, R91 U21 H1, H2, H3, H41 T1, T21 P21, P221
Description Header SMA Header BRES402 BRES402 ECLOSC MTHOLE6 Balun transformer Term strip
2 3 1 4 2 2
XX XX
M/A-COM Newark Electronics
ETC1-1-13
Parts not populated.
Rev. 0 | Page 27 of 28
AD9460 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.20 MAX
100 1 PIN 1
Preliminary Technical Data
16.00 BSC SQ 14.00 BSC SQ
76 75 76 75 100 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
9.50 SQ
1.05 1.00 0.95
0 MIN
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
25 26
50 49
51 50
BOTTOM VIEW (PINS UP) 26
25
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 22. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9460BSVZ-801 AD9460-80LVDS/PCB AD9460-105LVDS/PCB
1
Temperature Range -40C to +85C
Package Description 100-Lead TQFP_EP AD9460-80LVDS Mode Evaluation Board AD9460-105LVDS Mode Evaluation Board
Package Option SV-100-3
Z = Pb-free part.
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06006-0-3/06(PrA)
Rev. 0 | Page 28 of 28

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